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Freescale Semiconductor /MK61F15WS /ADC0 /CLP0

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Interpret as CLP0

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https://regviz.com/r/Freescale Semiconductor/MK61F15WS/ADC1/CLP0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLP00RESERVED

Description

ADC plus-side general calibration value register

Fields

CLP0

no description available
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data